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The new Bizen transistor architecture

The new Bizen transistor architecture

press Press 20 December 2019
“Semefab’s CEO, Allan James: The new Bizen transistor architecture can wind back the Moores’ Law clock by 10 years+, bringing many wafer fabs back into mainstream manufacture. Semefab and SFN are working flat out to make it a huge success.”
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BIT-TECH
UK startup teases CMOS-beating Bizen chip fab tech
DESIGN & ELEKTRONIK
Is a new type of bipolar taking CMOS from throne?
EET ASIA
The Combination of Bipolar-Zener Takes on CMOS
NTDHOY SPANISH
Thanks to the new process technology for transistor wafers Bizen uses the tunnel effect of quantum mechanics to allow complex ICs to be produced in “previous generations” plants.
BCBITI UKRAINE
The UK has developed a manufacturing process that is much better than CMOS
EPDT
Disruptive new wafer process technology to slash lead time winding back Moores Law
HACKADAY
The Bizen Transistor
BUSINESS WIRE
UK Collaboration unveils Bizen
ELECTRONICS MEDIA
uk collaboration unveils bizen a transistor wafer process technology
TECHWORKS NMI
Bizen - UK Collaboration presents an exciting new wafer process
YAHOO FINANCE
Search For The Next: UK Collaboration Unveils Bizen® a Transistor Wafer Process Technology Promising to Slash Lead Times, Wafer Area and Process Layers While Increasing Speed, Reducing Power and Increasing Gate Density Over CMOS
EE TIMES
Bipolar-Zener Combo Takes On CMOS
EE TIMES EUROPE
New Transistor Design Aims to Boost Business for UK Fabs
ELECTRONICS WEEKLY
Tunnelling transistor offers logic power easy IC
ELEKTRONIK PRAXIS GERMANY
Bizen is bigger than Brexit
ELECTRONICS SPECIFIER
Plugging the leak
IXBT RUSSIA
The UK has developed a process technology that is much better than CMOS
EENEWS
Bizen uses quantum tunnell mechanics
01NET
French publication - Extension of Moore's Law: The Incredible Promises of the Bizen Transistor
SILICON UK
Search For The Next: UK Collaboration Unveils Bizen® a Transistor Wafer Process Technology Promising to Slash Lead Times, Wafer Area and Process Layers While Increasing Speed, Reducing Power and Increasing Gate Density Over CMOS